Renesas Emulator System M3T-MR100 Manual de usuario descargar pdf (Pagina 13)

REJ05B1160-0101 Rev.1.01 February 2010 Page 13 of 43

M16C/62P Group, R32C/111 Group

Differences between M16C/62P and R32C/111 (100 pin ver.)

Table 4.14 Comparison Chart: Clock Characteristics (2/2)

Item M16C/62P R32C/111

Transition from on-chip oscillator

mode/on-chip oscillator low

power dissipation mode to stop

mode or wait mode

Enabled N/A

Transition from PLL self-

oscillation mode to stop mode or

wait mode

N/A Enabled: wait mode

Disabled: stop mode

CPU clock when exiting from

stop mode

Main clock divided by 8 Divide ratio of CPU clock when the

STOP instruction is executed

Table 4.15 Comparison Chart: Clock-associated Settings

Item M16C/62P R32C/111

XIN-XOUT drive power CM15 bit in the CM1 register Bits CM15 and CM16 in the CM1

Main clock division CM06 bit in the CM0 register and bits

CM17 and CM16 in the CM1 register

Bits CCD0 and CCD1 in the CCR

Base clock division N/A Bits BCD0 and BCD1 in the CCR

Peripheral bus clock division N/A Bits PCD0 and PCD1 in the CCR

PLL multiplexed ratio Bits PLC2 to PLC00 in the PLC0

Setting value of registers PLC0

and PLC1 specified in the

hardware manual

Table 4.16 Comparison Chart: Clock-associated Pin

Pin M16C/62P R32C/111

CLKOUT P5_7 P5_3

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 42 43

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Renesas Emulator System M3T-MR100 Manual de usuario Pagina 13