Renesas Emulator System M3T-MR100 Manual de usuario descargar pdf (Pagina 7)

REJ05B1160-0101 Rev.1.01 February 2010 Page 7 of 43

M16C/62P Group, R32C/111 Group

Differences between M16C/62P and R32C/111 (100 pin ver.)

4. Detailed Comparison

4.1 CPU Function

Table 4.1 to Table 4.6 list the changes from the M16C/62P on instructions, bit length of internal registers,

and flags.

Note:

1. These instructions are newly added with existing mnemonics. (Refer to Table 4.2).

Table 4.1 Chart: R32C/111 Instructions

Item R32C/111

Added instructions

ADDF, ADSF, BITINDEX, BRK2, CLIP, CMPF, CNVIF, DIVF, DIV

(1)

, DIVU

(1)

, DIVX

(1)

, EXITI, EXTZ, FREIT, INDEX Type, MAX, MIN, MUL

(1)

, MULU

(1)

, MULX, MULF,

ROUND, SCCnd, SCMPU, SIN, SMOVU, SOUT, STOP, SUBF, SUNTIL, and

SWHILE

Mnemonic changed

instructions

EDIV (from DIV), EDIVU (from DIVU), EDIVX (from DIVX), EMUL (from MUL), and

EMULU (from MULU)

Deleted instructions ADJNZ, BAND, BNAND, BNOR, BNTST, BNXOR, BOR, BXOR, JMPS, JSRS, LDE,

LDINTB, STE, and SBJNZ

Table 4.2 Comparison Chart: Mnemonic Changed Instructions and Their Bit Length (reference)

Mnemonic M16C/62P R32C/111

DIV, DIVU, DIVX 16 bit ÷ 8 bit = 8 bit (for byte)

32 bit ÷16 bit = 16 bit (for word)

8 bit ÷ 8 bit = 8 bit (for byte)

16 bit ÷16 bit = 16 bit (for word)

MUL, MULU 8 bit × 8 bit = 16 bit (for byte)

16 bit ×16 bit = 32 bit (for word)

8 bit × 8 bit = 8 bit (for byte)

16 bit ×16 bit = 16 bit (for word)

Table 4.3 Comparison Chart: Bit Processing Instructions (reference)

Mnemonic M16C/62P R32C/111

BSET Two-byte basis operation

BSET bit,R0 (bit = 0 to 15)

Example:

BSET bit,R0 (bit 0~15)

One-byte basis operation

BSET bit,R0L (bit = 0 to 7)

BSET bit,R0H (bit = 0 to 7)

Example:

BSET bit,R0L (bit 0~7)

BSET bit,R0H (bit 0~7)

1 2 3 4 5 6 7 8 9 10 11 12 ... 42 43

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