Renesas Emulator System M3T-MR100 Manual de usuario descargar pdf (Pagina 19)

REJ05B1160-0101 Rev.1.01 February 2010 Page 19 of 43

M16C/62P Group, R32C/111 Group

Differences between M16C/62P and R32C/111 (100 pin ver.)

4.8 Protection

Table 4.23 lists the changes on SFRs associated with the protection.

Table 4.23 Comparison Chart: Protection-associated SFRs

Symbol

Address

Bits M16C/62P R32C/111

M16C/62P R32C/111

PRCR 000Ah 4004Ah - Address changed

0 Protect bit 0:

Write enable to registers

CM0, CM1,CM2, PLC0, and

PCLKR

Protect bit 0:

Write enable to registers

CM0, CM1, CM2, and PM3

1 Protect bit 1:

Write enable to registers

PM0, PM1, PM2, TB2SC,

INVC0, and INVC1

Protect bit 1:

Write enable to registers

PM0. PM2, INVC0, INVC1,

IOBC, CSOP0, and CSOP1

2 Protect bit 2:

Write enable to registers

PD9, S3C, and S4C

Protect bit 2:

Write enable to registers

PD9, P9_iS (i = 3 to 7),

PLC0, and PLC1

3 Protect bit 3:

Write enable to registers

VCR2 and D4INT

N/A

PRCR2 N/A 4405Fh 7 N/A CM3 protect bit:

Write enable to the CM3

PRCR3 N/A 4004Ch 1 N/A Protect bit 31:

Write enable to registers

VRCR, LVDC, and DVCR

PRR N/A 0007h 7 to 0 N/A Write enable to registers CCR,

FMCR, PBC, FEBC0, FEBC3,

EBC0, EBC1, EBC2, EBC3,

CB01, CB12, and CB23:

AAh: write enabled

other than AAh: write

disabled

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 42 43

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