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MESC TECHNICAL NEWS

No.M16C-14-9805

( 1 / 3 )

GRADE

Precautions Regarding Writing to M16C/60, M16C/61, M16C/62 and

M16C/63 Group MCUs Interrupt Control Registers

1. Related devices

M16C/60, M16C/61, M16C/62 and M16C/63 groups

With the M16C/60 series MCU, setting the interrupt priority level and clearing the interrupt

request bit in the interrupt control registers should be done with interrupt disabled.

Executing these operations while interrupt is enabled may result in unintended CPU operations.

2. Symptom

Changing the Interrupt priority LeVeL select bit (ILVL) and clearing the Interrupt Request bit

(IR) in the Interrupt Control Registers (ICRs) while the Interrupt enable FLAG (I-FLAG) is "1"

may result in unintended operations, such as BRK and other interrupts being generated.

3. Considerations for writing new program

It is recommended that the interrupts must be disabled by clearing the I-FLAG, before setting

ILVL or clearing the IR bit in the ICRs.

In order to avoid the influence of the CPU pipeline, a certain number of instructions (eg. NOP)

should be inserted between writing to the ICRs and setting the I-FLAG.

The number of instructions (NOPs) required is shown in TABLE.

Related to M16C/60, M16C/20 series devices.

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Renesas Single-Chip Microcomputer M37531T-ADS Información técnica Pagina 28