Renesas Single-Chip Microcomputer M37531T-ADS Información técnica descargar pdf (Pagina 37)

MESC TECHNICAL NEWS

No.M16C-26-9905

( 1 / 1 )

GRADE

M16C/61 , M16C/62 Group

Precautions for UART2

1. Related devices

M16C/61 Group, M16C/62 Group

2. Precautions

When using UART2 in clock asynchronous serial I/O (UART) mode choose internal clock. If

UART2 in clock asynchronous mode is used with external clock, then one of the following may

occur;

2.1 The interrupt may not be issued at the end of data transmission when the hardware transfers

the data from the transmit buffer register to the transmit register.

2.2 Data may be corrupted when the hardware transfers the data from the transmit buffer

This precaution only applies to the UART2 asynchronous serial I/O mode and does not apply

to UART0 or UART1. It does not apply to any UART when used in the synchronous clocked

serial I/O mode.

Example of transmit with UART mode, Transfer data 8 bits long.

Start

bit

Parity

bit

Cleared to “0” when interrupt request is accepted, or cleared by software

Stop

bit

Data is set in UART2 transmit buffer register

Transferred from UART2 transmit buffer register to UARTi transmit registe

Transmit enable

bit(TE)

Transmit buffer

empty flag(TI)

Transmit register

empty flag (TXEPT)

“0”

“1”

“0”

“1”

“0”

“1”

Transmit interrupt

request bit (IR)

“0”

“1”

Transfer clock

TxD2

The above timing applies to the following settings :

• Parity is enabled.

• One stop bit.

• Transmit interrupt cause select bit = “0”.

Tc = 16 (n + 1) / fi

fi : frequency of BRG2 count source (f

, f

)

n : value set to BRG2

Shown in ( ) are bit symbols.

Note

Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.

Data may be corrupted

when external clock is

selected.

The interrupt request bit

may not be "1" when

external clock is selected.

Related to M16C/60, M16C/20 series devices.

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