Renesas Single-Chip Microcomputer M37531T-ADS Información técnica descargar pdf (Pagina 29)

No.M16C-14-9805

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Example 1

Example 2

Example 3

When not using HOLD function

Two NOP instructions required

No NOP instruction required (because there is dummy read)

No NOP instruction required

When using HOLD function

Four NOP instructions required

4. Conditions to be checked for program already written

Please confirm that at least one condition is met for both actions listed below. If any one of the

conditions is met, the symptom will not occur.

(1) When changing ILVL

- I-FLAG is "0". (Interrupt disabled) (*Note)

- The processor interrupt priority level (IPL) in the flag register is "7".

- The ILVL changes from a lower level than IPL to a higher level.

- The ILVL before and after the change is lower than IPL.

- The ILVL before and after the change is higher than IPL.

- It is obvious that the corresponding interrupt will not occur while changing the ILVL.

(2) When clearing the IR

- I-FLAG is "0". (Interrupt disabled) (*Note)

- The IPL in the flag register is "7".

- The ILVL during the operation is "0".

- The ILVL is lower than IPL.

- It is obvious that the corresponding interrupt will not occur while clearing the IR.

Note: In order to avoid the influence of the CPU pipeline, a certain number of instructions (eg.

NOP) should be inserted between writing to ICRs and setting the I-FLAG.

The number of instructions required is showed in the TABLE.

1 2 ... 24 25 26 27 28 29 30 31 32 33 34 ... 56 57

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Renesas Single-Chip Microcomputer M37531T-ADS Información técnica Pagina 29