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Renesas PCA4738L-64A Información técnica Pagina 27

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
24
TIMERS
The 3825 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0016”,
an underflow occurs at the next count pulse and the correspond-
ing timer latch is reloaded into the timer and the count is contin-
ued. When a timer underflows, the interrupt request bit corre-
sponding to that timer is set to “1”.
Read and write operation on 16-bit timer must be performed for
both high- and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct op-
eration when reading during the write operation, or when writing
during the read operation.
Fig. 19 Timer block diagram
CNTR
0
act
i
ve
edge switch bit
T
i
m
e
r
1
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
R
ea
l
t
i
me port
control bit “0”
“
1
”
P
5
5
/
CNTR
1
“0”
f(X
IN
)
/16
(
f
(
X
CIN
)
/16 in low-s
p
eed mode
]
)
C
N
T
R
1
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
“10”
Ti
mer
Y
stop
control bit
Falling edge detection
P
er
i
o
d
measurement mode
Ti
mer
Y
interrupt
request
Pulse width HL continuously measurement mode
Rising edge detection
“
0
0
”
,
“
0
1
”
,
“
1
1
”
T
i
m
e
r
Y
o
p
e
r
a
t
i
n
g
m
o
d
e
b
i
t
s
Ti
mer
X
interrupt
request
Ti
mer
X
mo
d
e reg
i
ster
write signal
P
5
4
/
C
N
T
R
0
Q
Q
T
S
P
5
4
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
u
l
se output mo
d
e
P
5
4
l
atc
h
T
i
m
e
r
X
s
t
o
p
c
o
n
t
r
o
l
b
i
t
“0”
“1”
T
i
m
e
r
X
w
r
i
t
e
c
o
n
t
r
o
l
b
i
t
Q
D
L
a
t
c
h
Q
D
L
a
t
c
h
“1”
“0”
“
1
”
“
1
0
”
Timer X operat-
ing mode bits
“00”,“01”,“11”
f
(
X
I
N
)
/
1
6
(
f
(
X
C
I
N
)
/
1
6
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
✽
)
P
u
l
se w
id
t
h
measurement
mode
C
N
T
R
0
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
P
u
l
se output mo
d
e
Q
Q
T
S
“0”
P
5
6
di
rect
i
on reg
i
ster
P
5
6
l
a
t
c
h
“
1
”
T
O
U
T
o
u
t
p
u
t
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
“
0
”
T
i
m
e
r
2
w
r
i
t
e
c
o
n
t
r
o
l
b
i
t
“0”
“1”
T
OUT
output
control bit
“
1
”
P
5
6
/
T
O
U
T
X
CIN
T
i
m
e
r
3
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
“0”
“
1
”
Ti
mer 2
interrupt
request
Ti
mer 3
interrupt
request
T
O
U
T
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
Ti
mer 2 count source
selection bit
Ti
mer 1
interrupt
request
D
a
t
a
b
u
s
f
(
X
I
N
)
/
1
6
(
f
(
X
C
I
N
)
/
1
6
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
]
)
f(X
IN
)/16
(
f
(
X
CIN
)
/16 in low-s
p
eed mode
]
)
f
(
X
IN
)
/16
(
f
(
X
CIN
)
/16 in low-s
p
eed mode
]
)
✽
Internal clock
φ
= X
CIN
/2.
CNTR
0
interrupt
request
C
N
T
R
1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
Ti
mer
Y
operat
i
ng mo
d
e
bi
t
s
“00”,“01”,“10
”
“11”
P
5
2
di
rect
i
on reg
i
ster “0”
R
e
a
l
t
i
m
e
p
o
r
t
c
o
n
t
r
o
l
b
i
t
“
1
”
P
5
2
P
5
2
l
a
t
c
h
P
5
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
“
0
”
R
ea
l
t
i
me port
control bit “1”
P
5
3
P
5
3
l
a
t
c
h
P
5
2
d
a
t
a
f
o
r
r
e
a
l
t
i
m
e
p
o
r
t
P
5
3
d
ata
f
or rea
l
t
i
me port
Timer Y (low) (8) Timer Y (high) (8)
Ti
mer 3
l
atc
h
(
8
)
Ti
mer 3
(
8
)
T
i
m
e
r
1
l
a
t
c
h
(
8
)
Ti
mer 1
(
8
)
T
i
m
e
r
2
l
a
t
c
h
(
8
)
Ti
mer 2
(
8
)
T
i
m
e
r
X
(
l
o
w
)
(
8
)
T
i
m
e
r
X
(
h
i
g
h
)
(
8
)
T
i
m
e
r
X
(
l
o
w
)
l
a
t
c
h
(
8
)T
i
m
e
r
X
(
h
i
g
h
)
l
a
t
c
h
(
8
)
Timer Y (low) latch (8) Timer Y (high) latch (8)
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