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Renesas PCA4738L-64A Información técnica Pagina 36

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
33
LCD DRIVE CONTROL CIRCUIT
The 3825 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
•
LCD display RAM
•
Segment output enable register
•
LCD mode register
•
Voltage multiplier
•
Selector
•
Timing controller
•
Common driver
•
Segment driver
•
Bias control circuit
A maximum of 40 segment output pins and 4 common output pins
can be used.
Up to 160 pixels can be controlled for LCD display. When the LCD
Fig. 30 Structure of segment output enable register and LCD mode register
enable bit is set to “1” after data is set in the LCD mode register,
the segment output enable register and the LCD display RAM, the
LCD drive control circuit starts reading the display data automati-
cally, performs the bias control and the duty ratio control, and dis-
plays the data on the LCD panel.
Table 10. Maximum number of display pixels at each duty ratio
Duty ratio Maximum number of display pixel
80 dots
or 8 segment LCD 10 digits
120 dots
or 8 segment LCD 15 digits
160 dots
or 8 segment LCD 20 digits
2
3
4
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e
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a
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e
b
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t
0
0
:
O
u
t
p
u
t
p
o
r
t
s
P
3
0–
P
35
1
:
S
e
g
m
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n
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u
t
p
u
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S
E
G1
8–
S
E
G2
3
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p
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n
a
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1
0
:
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P
3
6,
P
37
1
:
S
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m
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o
u
t
p
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S
E
G2
4,
S
E
G2
5
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t
o
u
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p
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n
a
b
l
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b
i
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2
0
:
O
u
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p
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p
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r
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s
P
0
0–
P
05
1
:
S
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p
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S
E
G2
6–
S
E
G3
1
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3
0
:
O
u
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p
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r
t
s
P
0
6,
P
07
1
:
S
e
g
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u
t
p
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S
E
G3
2,
S
E
G3
3
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p
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a
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4
0
:
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p
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P
1
0
1
:
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p
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S
E
G3
4
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m
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t
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t
p
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n
a
b
l
e
b
i
t
5
0
:
O
u
t
p
u
t
p
o
r
t
s
P
1
1–
P
15
1
:
S
e
g
m
e
n
t
o
u
t
p
u
t
S
E
G3
5–
S
E
G3
9
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
0
”
w
h
e
n
r
e
a
d
)
(
D
o
n
o
t
w
r
i
t
e
“
1
”
t
o
t
h
i
s
b
i
t
)
S
egment output ena
bl
e reg
i
ster
(SEG : address 0038
16)
b
7
b
0
LCD
mo
d
e reg
i
ster
(LM : address 0039
16)
D
uty rat
i
o se
l
ect
i
on
bi
ts
0 0 : Not used
0 1 : 2 duty (use COM
0, COM1)
1 0 : 3 duty (use COM
0–COM2)
1 1 : 4 duty (use COM
0–COM3)
Bias control bit
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Voltage multiplier control bit
0 : Voltage multiplier disable
1 : Voltage multiplier enable
LCD circuit divider division ratio selection bits
0 0 : Clock input
0 1 : 2 division of Clock input
1 0 : 4 division of Clock input
1 1 : 8 division of Clock input
LCDCK count source selection bit (Note)
0 : f(X
CIN)/32
1 : f(X
IN)/8192 (f(XCIN)/8192 in low-speed mode)
N
o
t
e
:
L
C
D
C
K
i
s
a
c
l
o
c
k
f
o
r
a
L
C
D
t
i
m
i
n
g
c
o
n
t
r
o
l
l
e
r
.
b
7
b
0
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