Renesas PCA4738L-64A Información técnica Pagina 67

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
64
Table 40. Timing reguirements 1 (M Version)
(V
CC = 4.0 to 5.5 V, VSS = 0 V, Ta = 20 to 85°C, unless otherwise noted.)
2
125
45
40
250
105
105
80
80
800
370
370
220
100
Note : When f(X
IN) = 8 MHz and bit 6 of address 001A16 is 1 (Clock synchronous).
Divide this value by four when f(X
IN) = 8 MHz and bit 6 of address 001A16 is 0 (UART).
Reset input L pulse width
Main clock input cycle time (X
IN input)
Main clock input H pulse width
Main clock input L pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input H pulse width
CNTR0, CNTR1 input L pulse width
INT0 to INT3 input H pulse width
INT0 to INT3 input L pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input H pulse width (Note)
Serial I/O clock input L pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
t
su(R
X
DS
CLK
)
t
h(S
CLK
R
X
D)
Symbol Parameter
Limits
Min.
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Typ. Max.
Table 41. Timing reguirements 2 (M Version)
(VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = 20 to 85°C, unless otherwise noted.)
Note: When f(X
IN) = 8 MHz and bit 6 of address 001A16 is 1 (Clock synchronous).
Divide this value by four when f(X
IN) = 8 MHz and bit 6 of address 001A16 is 0 (UART).
2
125
45
40
900 /
(V
CC 0.4)
450 /
(VCC 0.4) 20
450 /
(VCC 0.4) 20
230
230
2000
950
950
400
200
Reset input L pulse width
Main clock input cycle time (X
IN input)
Main clock input H pulse width
Main clock input L pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input H pulse width
CNTR0, CNTR1 input L pulse width
INT0 to INT3 input H pulse width
INT0 to INT3 input L pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input H pulse width (Note)
Serial I/O clock input L pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
t
su(R
X
DS
CLK
)
t
h(S
CLK
R
X
D)
Symbol Parameter
Limits
Min.
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Typ.
Max.
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