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Renesas PCA4738L-64A Información técnica Pagina 38

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
35
Voltage Multiplier (3 Times)
The voltage multiplier performs threefold boosting. This circuit in-
puts a reference voltage for boosting from LCD power input pin
V
L1. (However, when using a 1/2 bias, connect VL1 and VL2 and
apply voltage by external resistor division.)
The voltage multiplier control bit (bit 4 of the LCD mode register)
controls the voltage multiplier.
When voltage is input to the V
L1 pin during operating the voltage
multiplier, voltage that is twice as large as V
L1 occurs at the VL2
pin, and voltage that is three times as large as VL1 occurs at the
V
L3 pin.
When using the voltage multiplier; after applying 1.3 V ≤ Voltage ≤ 2.3 V
to the V
L1 pin, set the voltage multiplier control bit to “1” to select the
voltage multiplier enable.
When not using the voltage multiplier, apply proper voltage to the
LCD power input pins (VL1–VL3).
Bias Control and Applied Voltage to LCD
Power Input Pins
To the LCD power input pins (VL1–VL3), apply the voltage shown
in Table 11 according to the bias value.
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
Common Pin and Duty Ratio Control
The common pins (COM0–COM3) to be used are determined by
duty ratio.
Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the
LCD mode register).
Fig. 32 Example of circuit at each bias
Table 11. Bias control and applied voltage to VL1–VL3
Bias value
1/3 bias
1/2 bias
Voltage value
V
L3=VLCD
VL2=2/3 VLCD
VL1=1/3 VLCD
VL3=VLCD
VL2=VL1=1/2 VLCD
Note : VLCD is the maximum value of supplied voltage for the
LCD panel.
Table 12. Duty ratio control and common pins used
Duty
ratio
2
3
4
Common pins used
Notes 1: COM
2 and COM3 are open.
2: COM
3 is open.
Bit 1
0
1
1
Bit 0
1
0
1
COM
0, COM1 (Note 1)
COM
0–COM2 (Note 2)
COM
0–COM3
Duty ratio selection bits
V
L
3
V
L
2
C
2
C
1
V
L
1
1
/
3
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p
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V
L3
V
L2
C
2
C
1
V
L1
1
/
3
b
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R
2
R
1
R
3
R
1
=
R
2
=
R
3
C
ontrast contro
l
V
L
3
V
L
2
C
2
C
1
V
L
1
1/2
bi
as
O
p
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n
O
p
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R
4
R
5
R
4=
R
5
C
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c
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n
t
r
o
l
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