search

Renesas M3062PT2-EPB Manual de usuario Pagina 75

  • Descarga
  • Añadir a mis manuales
  • Imprimir
  • Pagina
    / 104
  • Tabla de contenidos
  • SOLUCIÓN DE PROBLEMAS
    •
  • MARCADORES
    • Valorado. / 5. Basado en revisión del cliente
Vista de pagina 74
M3062PT2-EPB User’s Manual 4. Hardware Specifications
R20UT0211EJ0300 Aug 16, 2012 Page 75 of 104
Rev.3.00
(2) Multiplex Bus Timing
Table 4.3 and Figure 4.2 show the bus timing in memory expansion mode and microprocessor mode (2-wait, accessing
external area, using multiplex bus).
Table 4.3 Memory expansion mode and microprocessor mode (2-wait, accessing external area, using multiplex bus)
Actual MCU
[ns]
This product
[ns]
Symbol Item
Min. Max. Min. Max.
td(BCLK-AD) Address output delay time 25 See left
th(BCLK-AD) Address output hold time (BCLK standard) 4 See left
th(RD-AD) Address output hold time (RD standard) (*1) (*4)
th(WR-AD) Address output hold time (WR standard) (*1) (*4)
td(BCLK-CS) Chip-select output delay time 25 See left
th(BCLK-CS) Chip-select output hold time (BCLK standard) 4 See left
th(RD-CS) Chip-select output hold time (RD standard) (*1) (*4)
th(WR-CS) Chip-select output hold time (WR standard) (*1) (*4)
td(BCLK-RD) RD signal output delay time 25 See left
th(BCLK-RD) RD signal output hold time 0 See left
td(BCLK-WR) WR signal output delay time 25 See left
th(BCLK-WR) WR signal output hold time 0 See left
td(BCLK-DB) Data output delay time (BCLK standard) 40 See left
th(BCLK-DB) Data output hold time (BCLK standard) 4 See left
td(DB-WR) Data output delay time (WR standard) (*2) See left
th(WR-DB) Data output hold time (WR standard) (*1) (*4)
td(BCLK-ALE) ALE output delay time (BCLK standard) 25 See left
th(BCLK-ALE) ALE output hold time (BCLK standard) -4 See left
td(AD-ALE) ALE output delay time (Address standard) (*3) See left
th(ALE-AD) ALE output hold time (Address standard) 30 See left
td(AD-RD) After address RD signal output delay time 0 See left
td(AD-WR) After address WR signal output delay time 0 See left
tdz(RD-AD) Address output floating start time 8 15
*1 Calculated by the following formula according to the frequency of BCLK.
)(
105.0
9
BCLKf
[ns]
*2 Calculated by the following formula according to the frequency of BCLK.

40
)(
105.0
9
BCLKf
n
[ns] n: "2" for 2 wait
*3 Calculated by the following formula according to the frequency of BCLK.
25
)(
105.0
9
BCLKf
[ns]
*4 Calculated by the following formula according to the frequency of BCLK.
12
)(
105.0
9
BCLKf
[ns]
Vista de pagina 74
1 2 ... 70 71 72 73 74 75 76 77 78 79 80 ... 103 104

Comentarios a estos manuales

Sin comentarios
Relacionado con productos y manuales para Redes Renesas M3062PT2-EPB
Redes Renesas M16C/64 Ficha de datos   (92 paginas)
Redes Renesas 740 Family Manual de usuario   (124 paginas)
Redes Renesas CPU Board M3A-HS19 Información técnica   (74 paginas)
Redes Renesas MCU Signal Measurement Board PCA7759 Manual de usuario   (8 paginas)
Redes Renesas H8S/2378F Información técnica   (109 paginas)
  • Poli Bracket Two-brothers-racing Salicru Dream Catcher Franger
  • Linksys Conectores de cable Artsound Altavoces Equator Secadoras Tripp Lite Cables de red American Standard Adaptadores De Interfaz / Cable De Género
  • ViewSonic PJD6210-WH Vitek VT-1761 Uniden BCD996T Motorola C118 Sony CCD-TR840E
  • Navman ICN 550 Manual de usuario GE Criterion Folleto Garmin GMI 20 Marine Instrument Manual de inicio rápido AEG LAVW1250 Manual de usuario Philips Power2Go Manual de usuario