Renesas M3062PT2-EPB Manual de usuario descargar pdf (Pagina 82)

M3062PT2-EPB User’s Manual 4. Hardware Specifications

R20UT0211EJ0300 Aug 16, 2012 Page 82 of 104

Rev.3.00

(3) Timing Requirements

Table 4.7 and Figures 4.6 show timing requirements in memory expansion mode and microprocessor mode.

Table 4.7 Timing requirements

Actual MCU

[ns]

This product

[ns]

Symbol Item

Min. Max. Min. Max.

tsu(DB-RD) Data input setup time 50 65

tsu(RDY-BCLK) RDY# input setup time 40 60

tsu(HOLD-BCLK) HOLD# input setup time 50 70

th(RD-DB) Data input hold time 0 See left

th(BCLK-RDY) RDY# input hold time 0 See left

th(BCLK-HOLD) HOLD# input hold time 0 See left

td(BCLK-HLDA) HLDA# output delay time 40 See left

Figure 4.6 Timing requirements

* Compared with an actual MCU, this product enters high-impedance state after a 0.5 cycle delay.

Common to “with wait” and “no wait” (actual MCU)

Hi-Z

BCLK

HOLD input

HLDA output

P0,P1,P2,P3,P4,

0 - P5 2

tsu(HOLD-BCLK)

td(BCLK-HLDA)

th(BCLK-HOLD)

Hi-Z

BCLK

HOLD input

HLDA output

P0,P1,P2,P3,P4,

0 - P5 2

tsu(HOLD-BCLK)

td(BCLK-HLDA)

th(BCLK-HOLD)

Common to “with wait” and “no wait” (this product)

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