Renesas M3062PT2-EPB Manual de usuario descargar pdf (Pagina 78)

M3062PT2-EPB User’s Manual 4. Hardware Specifications

R20UT0211EJ0300 Aug 16, 2012 Page 78 of 104

Rev.3.00

4.2.2 Operation Timing of Memory Expansion Mode and Micro

processor Mode (Vcc1=Vcc2=3V)

(1) Separate Bus Timing

Table 4.5 and Figure 4.4 show the bus timing in memory expansion mode and microprocessor mode (3 wait, accessing external

area).

Table 4.5 Memory expansion mode and microprocessor mode (3 wait, accessing external area)

Actual MCU

[ns]

This product

[ns]

Symbol Item

Min. Max. Min. Max.

td(BCLK-AD) Address output delay time 30 See left

th(BCLK-AD) Address output hold time (BCLK standard) 4 See left

th(RD-AD) Address output hold time (RD standard) 0 -6

th(WR-AD) Address output hold time (WR standard) (*2) (*3)

td(BCLK-CS) Chip-select output delay time 30 See left

th(BCLK-CS) Chip-select output hold time (BCLK standard) 4 See left

td(BCLK-ALE) ALE signal output delay time 30 See left

th(BCLK-ALE) ALE signal output hold time -4 See left

td(BCLK-RD) RD signal output delay time 30 See left

th(BCLK-RD) RD signal output hold time 0 See left

td(BCLK-WR) WR signal output delay time 30 See left

th(BCLK-WR) WR signal output hold time 0 See left

td(BCLK-DB) Data output delay time (BCLK standard) 40 See left

th(BCLK-DB) Data output hold time (BCLK standard) 4 See left

td(DB-WR) Data output delay time (WR standard) (*1) See left

th(WR-DB) Data output hold time (WR standard) (*2) (*3)

*1 Calculated by the following formula according to the frequency of BCLK.



)(

105.0





BCLKf

[ns] n: "3" for 3 wait

*2 Calculated by the following formula according to the frequency of BCLK.

)(

105.0

BCLKf



[ns]

*3 Calculated by the following formula according to the frequency of BCLK.

)(

105.0





BCLKf

[ns]

1 2 ... 73 74 75 76 77 78 79 80 81 82 83 ... 103 104

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