Renesas H8S/2111B Manual de usuario descargar pdf (Pagina 200)

100

101

Rev. 1.00, 05/04, page 166 of 544

9.3.8 Timer Control Register (TCR)

TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer

mode, and selects the FRC clock source.

Bit Bit Name

Initial

Value R/W Description

7 IEDGA 0 R/W Input Edge Select A

Selects the rising or falling edge of the input capture A

signal (FTIA).

0: Capture on the falling edge of FTIA

1: Capture on the rising edge of FTIA

6 IEDGB 0 R/W Input Edge Select B

Selects the rising or falling edge of the input capture B

signal (FTIB).

0: Capture on the falling edge of FTIB

1: Capture on the rising edge of FTIB

5 IEDGC 0 R/W Input Edge Select C

Selects the rising or falling edge of the input capture C

signal (FTIC).

0: Capture on the falling edge of FTIC

1: Capture on the rising edge of FTIC

4 IEDGD 0 R/W Input Edge Select D

Selects the rising or falling edge of the input capture D

signal (FTID).

0: Capture on the falling edge of FTID

1: Capture on the rising edge of FTID

3 BUFEA 0 R/W Buffer Enable A

Selects whether ICRC is to be used as a buffer register

for ICRA.

0: ICRC is not used as a buffer register for ICRA

1: ICRC is used as a buffer register for ICRA

2 BUFEB 0 R/W Buffer Enable B

Selects whether ICRD is to be used as a buffer register

for ICRB.

0: ICRD is not used as a buffer register for ICRB

1: ICRD is used as a buffer register for ICRB

1 2 ... 195 196 197 198 199 200 201 202 203 204 205 ... 581 582

Comentarios a estos manuales

Sin comentarios

Renesas H8S/2111B Manual de usuario Pagina 200

Comentarios a estos manuales

Relacionado con productos y manuales para Hardware Renesas H8S/2111B