Renesas H8S/2111B Manual de usuario descargar pdf (Pagina 255)

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WDT0102A_020020040200 Rev. 1.00, 05/04, page 221 of 544

Section 11 Watchdog Timer (WDT)

This LSI incorporates two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer

can generate an internal reset signal or an internal NMI interrupt signal if a system crash prevents

the CPU from writing to the timer counter, thus allowing it to overflow. Simultaneously, it can

output an overflow signal (RESO) externally.

When this watchdog function is not needed, the WDT can be used as an interval timer. In interval

timer operation, an interval timer interrupt is generated each time the counter overflows. A block

diagram of the WDT_0 and WDT_1 is shown in figure 11.1.

11.1 Features

• Selectable from eight (WDT_0) or 16 (WDT_1) counter input clocks.

• Switchable between watchdog timer mode and interval timer mode

Watchdog Timer Mode:

• If the counter overflows, an internal reset or an internal NMI interrupt is generated.

• When the LSI is selected to be internally reset at counter overflow, a low level signal is output

from the RESO pin if the counter overflows.

Internal Timer Mode:

• If the counter overflows, an internal timer interrupt (WOVI) is generated.

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Renesas H8S/2111B Manual de usuario Pagina 255

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