Renesas H8S/2111B Manual de usuario Pagina 251
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- MARCADORES
Valorado. / 5. Basado en revisión del cliente
Rev. 1.00, 05/04, page 217 of 544
10.10.3 Conflict between TCOR Write and Compare-Match
If a compare-match occurs during the T
2
state of a TCOR write cycle as shown in figure 10.16, the
TCOR write takes priority and the compare-match signal is disabled. With TMR_X, and TMR_A,
a TICR input capture conflicts with a compare-match in the same way as with a write to TCORC.
In this case also, the input capture takes priority and the compare-match signal is disabled.
φ
Address TCOR address
Internal write signal
TCNT
TCOR N M
TCOR write cycle by CPU
TCOR write data
N N + 1
Compare-match signal
Disabled
Note: * TMR_A, TMR_B
T
1
T
2
T
3
*
Figure 10.16 Conflict between TCOR Write and Compare-Match
10.10.4 Conflict between Compare-Matches A and B
If compare-matches A and B occur at the same time, the operation follows the output status that is
defined for compare-match A or B, according to the priority of the timer output shown in table
10.8.
Table 10.8 Timer Output Priorities
Output Setting Priority
Toggle output High
1 output
0 output
No change Low
- H8S/2111B 1
- Configuration of This Manual 5
- Preface 6
- Contents 9
- Figures 23
- Section 1 Overview 35
- 1.2 Internal Block Diagram 36
- 1.3 Pin Description 37
- 1.3.3 Pin Functions 43
- Table 1.2 Pin Functions 43
- Section 2 CPU 47
- 2.2 CPU Operating Modes 50
- Exception 51
- (Reserved for system use) 51
- Reserved 53
- 2.3 Address Space 54
- 2.4 Register Configuration 55
- SP (ER7) 57
- Free area 57
- Stack area 57
- 2.5 Data Formats 60
- 2.6 Instruction Set 63
- General register contents 78
- Don't care 79
- 2.8 Processing States 80
- External interrupt 81
- 2.9 Usage Notes 82
- 3.2 Register Descriptions 86
- 4.3 Reset 95
- Advanced mode 98
- Condition code register 99
- Program counter 99
- General register R1L 99
- Stack pointer 99
- 5.1 Features 101
- 5.2 Input/Output Pins 102
- 5.3 Register Descriptions 103
- • ISCRH 106
- • ISCRL 106
- • KMIMRA 108
- • KMIMR 108
- • WUEMRB 108
- 5.4 Interrupt Sources 110
- Vector Address 113
- Hold pending 115
- An interrupt with interrupt 118
- (1) (5) (7) (9) (11) (13) 119
- 5.7 Address Break 121
- 5.8 Usage Notes 124
- 6.1 Register Descriptions 127
- Section 7 I/O Ports 129
- Table 7.1 Port Functions 130
- 7.1 Port 1 134
- 7.2 Port 2 136
- 7.3 Port 3 138
- 7.4 Port 4 141
- • (IIC1AS+IIC1BS)* 143
- 7.5 Port 5 144
- 7.6 Port 6 146
- 7.7 Port 7 151
- 7.8 Port 8 152
- 7.9 Port 9 156
- • (IIC0AS+IIC0BS)* 157
- 7.10 Port A 159
- 7.11 Port B 163
- 7.12 Ports C, D 166
- 7.13 Ports E, F 170
- 7.14 Port G 176
- 8.1 Features 181
- 8.2 Input/Output Pins 182
- 8.3 Register Descriptions 182
- 8.4 Operation 187
- No additional pulse 188
- 8.4.1 PWM Setting Example 189
- 8.5 Usage Notes 190
- 9.1 Features 191
- Module data bus 192
- 9.2 Input/Output Pins 193
- 9.3 Register Descriptions 193
- 9.4 Operation 203
- 9.5 Operation Timing 204
- 9.5.3 FRC Clear Timing 205
- Input capture 206
- Input capture signal 206
- Overflow signal 209
- FRC H'FFFF H'0000 209
- 9.6 Interrupt Sources 211
- 9.7 Usage Notes 211
- New data 213
- 2 Switching from 214
- 4 Switching from 215
- 10.1 Features 217
- Table 10.1 TMR Function 218
- Internal bus 219
- 10.2 Input/Output Pins 222
- 10.3 Register Descriptions 223
- TCSR_0 230
- TCSR_Y 232
- TCSR_X 233
- TCSR_B 234
- TCSR_A 235
- 10.4 Operation 240
- 10.5 Operation Timing 241
- Compare-match A 242
- TCNT H'FF 243
- TICRR, TICRF read cycle 247
- 10.9 Interrupt Sources 249
- 10.10 Usage Notes 250
- Disabled 251
- 11.1 Features 255
- 11.2 Input/Output Pins 257
- 11.3 Register Descriptions 257
- • TCSR_0 258
- • TCSR_1 259
- 11.4 Operation 261
- TCNT value 262
- 11.5 Interrupt Sources 264
- 11.6 Usage Notes 265
- This LSI 267
- Reset input 267
- 12.1 Features 269
- 12.2 Input/Output Pins 270
- 12.3 Register Descriptions 271
- Mode Bit Rate Error 278
- Asynchronous mode 278
- Transmit/receive data 283
- 12.4.1 Data Transfer Format 284
- Formula (1) 285
- (Asynchronous Mode) 286
- D0 D1 D7 0/1 1 0 D0 D1 288
- <End> 292
- Transmitting 293
- Bit, One Stop Bit) 295
- Serial data 298
- Synchronization 298
- 12.7 Interrupt Sources 305
- 12.8 Usage Notes 306
- Port input/output 308
- Transmission start 308
- (Internal Clock) 309
- Section 13 I 311
- C Bus Interface (IIC) 311
- C Bus Interface 312
- Figure 13.2 I 313
- 13.2 Input/Output Pins 314
- 13.3 Register Descriptions 315
- 13.3.4 I 320
- C Bus Mode Register (ICMR) 320
- Table 13.3 I 322
- C Transfer Rate 322
- 13.3.5 I 323
- ICCR controls the I 323
- 13.3.6 I 331
- C Bus Status Register (ICSR) 331
- 13.3.8 I 336
- 13.4 Operation 341
- Figure 13.5 I 342
- C Bus Timing 342
- Table 13.6 I 342
- C Bus Data Format Symbols 342
- 13.4.2 Initialization 343
- [1] Initialization 344
- (master output) 347
- (slave output) 347
- 21436587989 347
- (HNDS = 1) 348
- (MLS = WAIT = 0, HNDS = 1) 350
- Clear IRIC flag in ICCR 351
- Read ICDR 351
- Set HNDS = 0 in ICXR 352
- Set WAIT = 0 in ICMR 352
- (MLS = ACKB = 0, WAIT = 1) 354
- Slave receive mode 356
- (MLS = 0, HNDS= 1) 358
- for the last reception 359
- [15] Clear IRIC 359
- [12] Detect stop condition 359
- (MLS = ACKB = 0, HNDS = 0) 361
- Clear IRIC in ICCR 362
- Set TRS = 0 in ICCR 362
- (MLS = 0) 364
- C bus format, wait inserted) 366
- User processing 367
- System clock 368
- 13.5 Interrupt Sources 370
- 13.6 Usage Notes 371
- Table 13.10 I 373
- Confirmation of stop 374
- condition issuance 374
- (read BBSY = 0) 374
- [1] SCL = low determination 377
- [2] IRIC clear 377
- R/W ASLA 381
- 14.1 Features 383
- 14.2 Input/Output Pins 384
- 14.3 Register Descriptions 385
- 14.4 Operation 389
- Receive 392
- 14.4.7 Receive Timing 397
- 14.5 Usage Notes 399
- 15.1 Features 401
- 15.2 Input/Output Pins 403
- 15.3 Register Descriptions 404
- • HICR0 405
- • HICR1 408
- • HICR3 412
- • STR1 416
- • STR2 417
- • SIRQCR0 421
- • SIRQCR1 424
- 15.4 Operation 430
- Master will 432
- At least 60 µs 438
- Pull-up enable 441
- 15.5 Interrupt Sources 442
- 15.6 Usage Notes 445
- Section 16 A/D Converter 447
- Successive approximations 448
- Multiplexer 448
- Bus interface 448
- 16.2 Input/Output Pins 449
- 16.3 Register Descriptions 450
- 16.4 Operation 453
- State of channel 2 (AN2) 454
- 16.5 Interrupt Sources 457
- Nonlinearity 458
- 16.7 Usage Notes 459
- To A/D converterAN0 to AN5 461
- Section 17 RAM 463
- Section 18 ROM 465
- • Programmer mode 466
- 18.2 Mode Transitions 467
- Figure 18.3 Boot Mode 468
- Boot program 469
- 18.3 Block Configuration 470
- 18.4 Input/Output Pins 471
- 18.5 Register Descriptions 471
- 18.6 Operating Modes 475
- ItemBoot mode start 477
- Bit rate adjustment 477
- Flash memory erase 477
- Transfer of programming 477
- Possible 478
- Program/erase? 479
- End of programming 481
- Set block start address 483
- 18.11 Programmer Mode 486
- 18.12 Usage Notes 487
- Subclock 489
- 19.1 Oscillator 490
- 19.5 Subclock Input Circuit 494
- 19.7 Clock Select Circuit 495
- 19.8 Usage Notes 495
- 20.1 Register Descriptions 497
- • MSTPCRH 501
- • MSTPCRL 501
- 20.3 Medium-Speed Mode 504
- 20.4 Sleep Mode 505
- 20.5 Software Standby Mode 505
- NMI exception 506
- 20.6 Hardware Standby Mode 507
- 20.7 Watch Mode 508
- 20.8 Subsleep Mode 509
- 20.9 Subactive Mode 510
- 20.10 Module Stop Mode 511
- 20.11 Direct Transitions 511
- 20.12 Usage Notes 512
- 21.2 Register Bits 523
- 22.2 DC Characteristics 548
- Darlington pair 552
- Ports 1 to 3 553
- 22.3 AC Characteristics 554
- — — ±7.5 LSB 560
- 22.6 Usage Note 563
- (i = 0, 1, 2, 6, 7) 564
- Ports 1 to 9, and A to G 566
- TMRI0, TMRI1 567
- TMIX, TMIY 567
- ExTMIX, ExTMIY 567
- TMIA, TMIB 567
- TxD1, ExTxD1 568
- (transmit data) 568
- Figure 22.22 I 569
- LAD3 to LAD0 570
- SERIRQ, CLKRUN 570
- (Transmit signal) 570
- Appendix 571
- B. Product Codes 572
- C. Package Dimensions 573
- Hardware Manual 579
- RENESAS SALES OFFICES 580
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