Renesas H8S/2111B Manual de usuario descargar pdf (Pagina 511)

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Rev. 1.00, 05/04, page 477 of 544

20.10 Module Stop Mode

Module stop mode can be individually set for each on-chip peripheral module.

When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of

the bus cycle and a transition is made to module stop mode. In turn, when the corresponding

MSTP bit is cleared to 0, module stop mode is cancelled and the module operation resumes at the

end of the bus cycle. In module stop mode, the internal states of modules other than the SCI and

PWM are retained.

After the reset state is cancelled, all modules are in module stop mode.

While an on-chip peripheral module is in module stop mode, read/write access to its registers is

disabled.

20.11 Direct Transitions

The CPU executes programs in three modes: high-speed, medium-speed, and subactive. When a

direct transition is made from high-speed mode to subactive mode, there is no interruption of

program execution. A direct transition is enabled by setting the DTON bit in LPWRCR to 1 and

then executing the SLEEP instruction. After a transition, direct transition exception handling

starts.

The CPU makes a transition to subactive mode when the SLEEP instruction is executed in high-

speed mode with the SSBY bit in SBYCR set to 1, the LSON bit and DTON bit in LPWRCR set

to 11, and the PSS bit in TSCR (WDT_1) set to 1.

To make a direct transition to high-speed mode after the time set in the STS2 to STS0 bits in

SBYCR has elapsed, execute the SLEEP instruction in subactive mode with the SSBY bit in

SBYCR set to 1, the LSON bit and DTON bit in LPWRCR set to 01, and the PSS bit in TSCR

(WDT_1) set to 1.

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