Renesas H8S/2111B Manual de usuario descargar pdf (Pagina 421)

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Rev. 1.00, 05/04, page 387 of 544

15.3.8 SERIRQ Control Registers 0 and 1 (SIRQCR0, SIRQCR1)

The SIRQCR registers contain status bits that indicate the SERIRQ operating mode and bits that

specify SERIRQ interrupt sources.

• SIRQCR0

R/W

Bit Bit Name

Initial

Value

Slave Host Description

7 Q/C 0 R — Quiet/Continuous Mode Flag

Indicates the mode specified by the host at the end of

an SERIRQ transfer cycle (stop frame).

0: Continuous mode

[Clearing conditions]

• LPC hardware reset, LPC software reset

• Specification by SERIRQ transfer cycle stop frame

1: Quiet mode

[Setting condition]

• Specification by SERIRQ transfer cycle stop frame.

6 SELREQ 0 R/W — Start Frame Initiation Request Select

Selects whether start frame initiation is requested when

one or more interrupt requests are cleared, or when all

interrupt requests are cleared, in quiet mode.

0: Start frame initiation is requested when all interrupt

requests are cleared in quiet mode.

1: Start frame initiation is requested when one or more

interrupt requests are cleared in quiet mode.

5 IEDIR 0 R/W — Interrupt Enable Direct Mode

Specifies whether LPC channel 2 and channel 3

SERIRQ interrupt source (SMI, IRQ6, IRQ9 to IRQ11)

generation is conditional upon OBF, or is controlled only

by the host interrupt enable bit.

0: Host interrupt is requested when host interrupt enable

bit and corresponding OBF are both set to 1

1: Host interrupt is requested when host interrupt enable

bit is set to 1

1 2 ... 416 417 418 419 420 421 422 423 424 425 426 ... 581 582

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