Renesas Renasas Single-Chip Microcomputer SH7086 Manual de usuario descargar pdf (Pagina 270)

252

Chapter 5 Interrupt

When the processor interrupt priority level (IPL) or the interrupt priority level of some interrupt is

changed, the altered level is reflected in interrupt handling at the following timing:

• If the processor interrupt priority level (IPL) is changed by an REIT instruction, the changed level takes

effect beginning with the instruction that is executed two clock periods after the last clock of the REIT

instruction.

• If the processor interrupt priority level (IPL) is changed by a POPC, LDC, or LDIPL instruction, the

changed level takes effect beginning with the instruction that is executed three clock periods after the

last clock of the instruction used.

• If the interrupt priority level of a particular interrupt is changed by an instruction such as MOV, the

changed level takes effect beginning with the instruction that is executed two clock or three clock

periods after the last clock of the instruction used.

M16C/60, M16C/61 group, and M16C/20 series: two clock

M16C/60 series after M16C/62 group (it has M16C/62 group), M16C/Tiny series : three clock

5.2.3 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)

Interrupt priority levels are set by the interrupt priority select bit in an interrupt control register. When an

interrupt request is generated, the interrupt priority level of this interrupt is compared with the processor

interrupt priority level (IPL). This interrupt is enabled only when its interrupt priority level is greater than

the processor interrupt priority level (IPL). This means that you can disable any particular interrupt by

setting its interrupt priority level to 0.

Table 5.2.1 shows how interrupt priority levels are set. Table 5.2.2 shows interrupt enable levels in

relation to the processor interrupt priority level (IPL).

The following lists the conditions under which an interrupt request is acknowledged:

• Interrupt enable flag (I flag) = 1

• Interrupt request bit = 1

• Interrupt priority level > Processor interrupt priority level (IPL)

The interrupt enable flag (I flag), interrupt request bit, interrupt priority level select bit, and the processor

interrupt priority level (IPL) all are independent of each other, so they do not affect any other bit.

0 1 0

0 1 1

1 1 0

1 1 1

0 0 1

0 0 0

Low

High

1 0 1

1 1 0

1 1 1

0 0 0

1 0 0

0 0 1

0 1 0

0 1 1

Table 5.2.2 IPL and Interrupt Enable LevelsTable 5.2.1 Interrupt Priority Levels

Interrupt priority

level select bit

Interrupt priority

level

Priority

order

b0b1b2

1 0 0

1 0 1

Processor interrupt

priority level (IPL)

Enabled interrupt priority

levels

IPL

nterrupt levels 1 and above are enabled.

Interrupt levels 2 and above are enabled.

Interrupt levels 3 and above are enabled.

Interrupt levels 4 and above are enabled.

Interrupt levels 5 and above are enabled.

Interrupt levels 6 and above are enabled.

Interrupt levels 7 and above are enabled.

All maskable interrupts are disabled.

Level 0

(interrupt disabled)

Level 1

Level 2

Level 3

Level 4

Level 5

Level 6

Level 7

IPL

5.2 Interrupt Control

1 2 ... 265 266 267 268 269 270 271 272 273 274 275 ... 307 308

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