Renesas Renasas Single-Chip Microcomputer SH7086 Manual de usuario descargar pdf (Pagina 273)

255

Chapter 5 Interrupt

5.3.1 Interrupt Response Time

The interrupt response time means a period of time from when an interrupt request is generated till when

the first instruction of the interrupt routine is executed. This period consists of time (a) from when an

interrupt request is generated to when the instruction then under way is completed and time (b) in which

an interrupt sequence is executed. Figure 5.3.1 shows the interrupt response time.

Table 5.3.1 Interrupt Sequence Execution Time

Time (a) varies with each instruction being executed. The DIVX instruction requires a maximum time

that consists of 30 cycles (without wait state) .

Time (b) is shown below.

Figure 5.3.1. Interrupt response time

(a)

(b)

Time

Instruction

Interrupt response time

Instruction in interrupt

routine

Interrupt sequence

Interrupt request acknowledged

Interrupt request generated

(a)

Time from when interrupt request is generated to when the instruction then under execution is completed

(b) Time in which the interrupt sequence is executed

8 bits data bus

Without wait state

20 cycle

16 bits data bus

Without wait state

18 cycle

19 cycle

20 cycle

Stack pointer (SP) value

Even address

Odd address

Even address

Odd address

5.3 Interrupt Sequence

________

*1 Add two cycles for the DBC interrupt. Add one cycle for the address match and single-step interrupts.

*2 Allocate interrupt vector addresses in even addresses as must as possible.

Interrupt vector address

Even address

Odd address

1 2 ... 268 269 270 271 272 273 274 275 276 277 278 ... 307 308

Comentarios a estos manuales

Sin comentarios

Renesas Renasas Single-Chip Microcomputer SH7086 Manual de usuario Pagina 273

Comentarios a estos manuales

Relacionado con productos y manuales para Redes Renesas Renasas Single-Chip Microcomputer SH7086