Renesas Renasas Single-Chip Microcomputer SH7086 Manual de usuario descargar pdf (Pagina 87)

3.2 Functions

Chapter 3 Functions

DIVide eXtension

Singed divide

[ Syntax ]

DIVX.size src

[ Description Example ]

[ Related Instructions ] DIV,DIVU,MUL,MULU

DIVX DIVX

DIVX.B A0 ;A0’s 8 low-order bits is the divisor.

DIVX.B #4

DIVX.W R0

B , W

[ Operation ]

If the size specifier (.size) is (.B)

R0L (quotient), R0H (remainder) R0 src

If the size specifier (.size) is (.W)

R0 (quotient), R2 (remainder) R2R0 src

[ Flag Change ]

UIOBSZDC

Flag

Conditions

O : The flag is set when the operation resulted in the quotient exceeding 16 bits (.W) or 8 bits (.B) or

the divisor is 0; otherwise cleared.

[ Function ]

•

This instruction divides R2R0 (R0)

by signed

src

and stores the quotient in R0 (R0L)

and the remainder in R2

(R0H)

. The remainder has the same sign as the divisor. Shown in ( )

are the registers that are operated on

when you selected (.B) for the size specifier (.size).

• If

src

is an A0 or A1 when the size specifier (.size) you selected is (.B), operation is performed on the

8 low-order bits of A0 or A1.

• If you specify (.B) for the size specifier (.size), the O flag is set when the operation resulted in the

quotient exceeding 8 bits or the divisor is 0. At this time, R0L and R0H are indeterminate.

• If you specify (.W) for the size specifier (.size), the O flag is set when the operation resulted in the

quotient exceeding 16 bits or the divisor is 0. At this time, R0 and R2 are indeterminate.

src

R0L/R0 R0H/R1 R1L/R2 R1H/R3

A0/A0 A1/A1 [A0] [A1]

dsp:8[A0] dsp:8[A1] dsp:8[SB] dsp:8[FB]

dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16

dsp:20[A0] dsp:20[A1] abs20 #IMM

R2R0 R3R1 A1A0

[ Selectable src ]

Change

[ Instruction Code/Number of Cycles ]

Page=

174

1 2 ... 82 83 84 85 86 87 88 89 90 91 92 ... 307 308

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