Renesas Renasas Single-Chip Microcomputer SH7086 Manual de usuario descargar pdf (Pagina 272)

254

Chapter 5 Interrupt

5.3 Interrupt Sequence

An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the

instant the interrupt routine is executed — is described here.

If an interrupt occurs during execution of an instruction, the processor determines its priority when the

execution of the instruction is completed, and transfers control to the interrupt sequence from the next

cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,

the processor temporarily suspends the instruction being executed, and transfers control to the interrupt

sequence.

In the interrupt sequence, the processor carries out the following in sequence given:

(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address

0000016.

(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence

in the temporary register (Note) within the CPU.

(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to

“0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32

through 63, is executed)

(4) Saves the content of the temporary register (Note 1) within the CPU in the stack area.

(5) Saves the content of the program counter (PC) in the stack area.

(6) Sets the interrupt priority level of the accepted instruction in the IPL.

After the interrupt sequence is completed, the processor resumes executing instructions from the first ad-

dress of the interrupt routine.

Note: This register cannot be utilized by the user.

5.3 Interrupt Sequence

1 2 ... 267 268 269 270 271 272 273 274 275 276 277 ... 307 308

Sin comentarios

Renesas Renasas Single-Chip Microcomputer SH7086 Manual de usuario Pagina 272