Renesas Renasas Single-Chip Microcomputer SH7086 Manual de usuario descargar pdf (Pagina 278)

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Chapter 5 Interrupt

5.6 Multiple Interrupts

The following shows the internal bit states when control has branched to an interrupt routine:

• The interrupt enable flag (I flag) is cleared to 0 (interrupts disabled).

• The interrupt request bit for the acknowledged interrupt is cleared to 0.

•

The processor interrupt priority level (IPL) equals the interrupt priority level of the acknowledged interrupt.

By setting the interrupt enable flag (I flag) (= 1) in the interrupt routine, you can reenable interrupts so that an

interrupt request can be acknowledged that has higher priority than the processor interrupt priority level

(IPL). Figure 5.6.1 shows how multiple interrupts are handled.

The interrupt requests that have not been acknowledged for their low interrupt priority level are kept pend-

ing. When the IPL is restored by an REIT instruction and interrupt priority is resolved against it, the pending

interrupt request is acknowledged if the following condition is met:

Interrupt priority level of

pending interrupt request

Restored processor interrupt

priority level (IPL)

5.6 Multiple interrupts

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Renesas Renasas Single-Chip Microcomputer SH7086 Manual de usuario Pagina 278