Renesas SuperH SH7710 E10A Manual de usuario

SuperH® Family ofMicrocontrollers andMicroprocessors2006.4®

8SuperH®Family of Microcontrollers & Microprocessors Total upward code compatibilityThe roadmap for the SuperH processor productline is upwardly

Balanced power/performanceThe fast speeds that SuperH devices provide wouldnot be usable by portable applications if the chips’power dissipation was

10SuperH®Family of Microcontrollers & Microprocessors SuperH has 2D and 3Dgraphics capabilitiesSuperH RISC and RISC/FPUmicroprocessors have excel

Top Reasons To Select SuperH11 SuperH standard, off-the-shelf solutionsRenesas’ qualified middleware and provenreference boards comprise a complete s

Peripherals LCD Controller• From 16x1 to 800x600 pixels(SVGA) can be supported• 1/2/4/6/8/16 bpp (bit per pixel)with 18-bit color pallet• 1/2/4 bpp g

Peripherals Controller Area Network(CAN)• CAN version: Bosch 2.0B active compatible– Communication systems: NRZ(Non-Return to Zero) system (with bit-

Peripherals Peripheral Control Interconnect (PCI)• Compatible with PCI bus operatingspeeds of 33MHz/66MHz• Compatible with 32-bit PCI bus• Up to four

Peripherals• An interrupt request can be sent to the CPU on completion of the specified number of transfers• Various DMAC transfer requests are provid

Renesas’ Integrated Development EnvironmentThe High-performance EmbeddedWorkshop (or HEW) is a graphicaldevelopment environment forC/C++ compiler tool

HEW Profile Tree and Chart viewsProject Manager– Graphical control of compiler/linker options– Function browser– Drag-and-drop code templates– Built-i

IMPORTANT!• This document may, wholly or partially, be subject to change without notice.• All rights are reserved: No one is permitted to reproduce or

Optimized C/C++ code generationtoolchainsThe Renesas compiler toolchains(compiler, assembler and linker)support the full C++ languagespecification and

HardwareEvaluation and Development Kits Renesas’ low-cost Evaluation andDevelopment Kits (EDKs) are inex-pensive ways to experience the per-formance

multiple SuperH devices. Typicalfeatures of the Solution Engineinclude:• External flash for user code• EPROM containing monitor code• JTAG connector e

SuperH®Development Tools21functions in up to 4MB of the system addressspace (8 x 512K blocks). An optional profilingexpansion board increases the prof

Evaluation Chip UnitThe special “bond-out”chip on theoptional Evaluation Chip unitbrings out internal CPU buses,which – when used with the BusTrace un

SuperH®Development Tools23 Third-party Development ToolsMany third-party experts offer development toolssupported by design services, RTOS, compilers

FEATURESPERFORMANCESH-2ROM: 128-160KBRAM: 3-4KBSH7010SeriesSH2-DSPSH-DualSeriesAvailable NowNEWIn Planning20MHz 50MHz 80MHz 100MHz 120-200MHzROM: 64-1

SH-2 Series Selector GuideFamily Series Device NumberFlash (Kbytes)RAM (Kbytes)Vcc minVcc maxmax MHz @ Vcc maxPower Down Modes8-bit timers16-bit timer

FEATURESPERFORMANCESH-2 Single-channelEthernet ControllerSH3-DSPDual-ChannelEthernet ControllerSH-4Ether400MHzAvailable NowNEWIn PlanningEther, FIFO 5

SH-Ether Series Selector GuideFamily Series Device NumberRAM (Kbytes)Vcc minVcc maxmax MHz @ Vcc maxWatchdog TimerA/D 10-bit resolutionD/A 8-bit reso

H8 ArchitectureM16C Architecture32-Bit RISC• Highest performance• Highest integration32-Bit• Highest performance CISC16-Bit• High performance, high

FEATURESPERFORMANCESH3-DSPSH-4SH-4A800-1000MHzAvailable NowNEWIn PlanningSH7729R100/133/167/200MHzSH7780Series400-600MHzSH-4ASH-4A Ether400MHzGb-Ether

SH-3 Series Selector GuideFamily Series Device NumberRAM (Kbytes)Vcc minVcc maxmax MHz @ Vcc maxWatchdog TimerA/D 10-bit resolutionD/A 8-bit resoluti

30SH-3 and SH-4 Series (continued) SH-4 Features• Two-way superscalar support – top performance per MHz– Harvard architecture, RISC and FPUinstructio

Gb EthernetGb EthernetBroadbandModemInternetPCPCIWi-FiDDR-SDRAMControllerDDR-SDRAMLocal BusControllerFlashLCDControllerSoundInterfacesStreamInterfaceM

Appendices32BufferROMSH-2CPUDSPY-RAMUser breakcontrollerInterruptcontrollerBus statecontrollerClock pulsegeneratorSerialcommunicationinterfaceMotorman

33Architecture DiagramsCPU bus(C bus)(I clock)SH-2ACPU coreCachecontrollerInstructioncache memory8 KbytesOperandcache memory8 KbytesOn-chip RAM128 Kby

Appendices34LEGEND:ADC:ASERAM:AUD:BSC:CACHE:CCN:CMT:CPG/WDT:CPU:DAC:DMAC:DSP:UDI:INTC:A/D converterASE memoryAdvanced user debuggerBus state controlle

35Architecture DiagramsCPU I-cacheLBSC(External bus) LEGEND:AUD: CMT: CPG: CPU: DDRIF: DMAC: FLCTL: FPU: GPIO: HAC: HPB: HSPI: H-UDI: I-Cache: INTC: L

AppendicesHD64 X #### X X # X VDigital CMOS ProcessMaximum Speed (MHz)On-chip memory type: 1: ROMless 3: Masked ROM 7: OTP 8: EEPROM F: Flas

Appendices Appendix B-2: Nomenclature of SuperH Part Numbers (2 of 2)R X X 7### X X # X VRenesas LSIV: RoHS Compliant Package4: Existing Series5

The first 32-bit SuperH RISC device was introduced in1993. In the years since, this popular product line hascontinuously grown and steadily evolved. T

Appendices Appendix C: Abbreviations Appendix D: Package SpecificationsPrevious Pin Nominal Body Lead Pitch ThicknessType Renesas Code Code Count Di

Flip openfor Appendices.Renesas Interactive is a valuable FREE online evaluationservice that lets you work at your own pace, whenever it ismost conven

© 2006 Renesas Technology America, Inc. Renesas Technology America, Inc. is a wholly owned subsidiary of Renesas Technology Corporation. SuperH is a

Family Overview3SuperH Series Performance, Features and ApplicationsCore CPU/Bus Speed Performance Series Features / Remarks Key ApplicationsSH-2 80/4

SuperH Architecture:Common FeaturesRISC-type instruction set• Instruction length: fixed 16-bit-long instructions forimproved code efficiency• Load-s

Built in hardware multiply-accumulate unit• 16-bit x 16-bit + 42-bit (SH-1 devices)• 32-bit x 32-bit + 64-bit (SH-2, SH-3, SH-4 chips)Instruction exec

6SuperH®Family of Microcontrollers & Microprocessors SuperH Hybrid RISC/DSPArchitectural FeaturesInstruction set upward compatiblewith SuperH RIS

Hybrid RISC/DSP Architecture • Floating Point Features7 SuperH On-Chip Floating Point Co-processorArchitectural Features• Supports single-precision (