Renesas SuperH SH7710 E10A Manual de usuario descargar pdf (Pagina 14)

Peripherals

■ LCD Controller

• From 16x1 to 800x600 pixels

(SVGA) can be supported

• 1/2/4/6/8/16 bpp (bit per pixel)

with 18-bit color pallet

• 1/2/4 bpp grayscale

• 8-bit frame rate controller

• Supports data formats for

STN/dual-STN/TFT panels

(8/12/16/18-bit bus width)

• Supports variations of the burst

length in reading from the

synchronous DRAM to achieve

high data-read speeds

• Supports inversion of the output

signal, if necessary, to match the

LCD panel’s signal polarity

• Hardware-rotation mode is

included to support the use of

landscape-format LCD panels as

portrait-format LCD panels

• Power control function

• A unified memory architecture

is adopted for the LCD controller

so the image data for display is

stored in system memory

■ Ethernet MAC

• MAC (Media Access Control) functions

– Data frame assembly/disassembly

(IEEE802.3-compliant frame)

– CSMA/CD link management

(collision avoidance, processing in case of collision)

– CRC/PAD processing

– Built-in FIFO (2KB for Tx, 2KB for Rx)

– Supports full-duplex and half-duplex

transmission/reception

– Short packets/long packets

• Compatible with MII (Media Independent Interface)

standard

– Converts 8-bit data stream from MAC layer to MII nibble

data stream (4 bits)

– Station management (STA) functions

– 18 TTL-level signals (5V or 3.3V interface)

– Variable transfer rate: 10/100Mbps

(based on PHY chip features)

• Magic Packet

™

(with wake-on-LAN output)

• CAM (Contents Addressable Memory) Interface

SuperH

Family of Microcontrollers & Microprocessors

Clock

Generator

Pallet

RAM

512 bytes

LCDC

Power Control

LCLK

CKIO

P Clock

Bus Interface

Li Bus Interface

Li Bus

Line Buffer

2.4 kbytes

CL1

CL2

FLM

LCD 15

DON

VCPWC

VEPWC

M/DISP

clk

Peripheral

Bus

LCD Controller Block Diagram

MAC

Transmit Control

Receive Control

Command/Status

Interface

ECMR.DM

PIR

PSR.LMON

MII

Interface

PHY Chip

PHYSTS

LINK

MII

MDC/

MCIO

EtherC Function Block Diagram

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 41 42

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