Renesas SuperH SH7710 E10A Manual de usuario descargar pdf (Pagina 10)

8

SuperH

®

Family of Microcontrollers & Microprocessors

■ Total upward code compatibility

The roadmap for the SuperH processor product

line is upwardly code compatible. This

compatibility enables a faster time-to-market

with further amortization of prior engineering

investment and preservation of previously

written software.

• Processor choice from 10 to 1080 MIPS

• Large selection of devices within each family

■ Best code efficiency

• 16-bit instruction length for high code

density

• Up to 40% less memory footprint than

32-bit instructions

• Up to 40% more data in cache than

32-bit instructions

• Twice the number of instructions loaded

on the SDRAM bus

SH-1

SH-2

SH-3

SH-4

SuperH

Non-DSP

Instructions

DSP

Instruc-

tions

MIPS

NEC IDT

Toshiba

PowerPC

IBM

FreeScale

ARM

ARM7

Atmel/Cirrus

ARM9

FreeScale

XScale

Intel

Upward Code Compatibility

1.5

RELATIVE

VALUE

1.0

SuperH

(16-bit fixed)

1.24

V830

(32-bit variable)

1.28

MIPS64

(32-bit fixed)

1.44

ARM

(32-bit fixed)

1.5

PowerPC

(32-bit fixed)

0.5 1.0

C Object Size Comparison

SuperH Code Efficiency

Higher Execution

Performance

• Superscalar gives

1.5x more performance

at the same MHz

• SH-2A = 6x the

performance of SH-2

Faster Interrupt

Response Time

• SH-2: 37 cycles;

SH-2A: 6 cycles

• SH-2A = 1/25 the

response time of SH-2

Denser Program Code Size

• Improved C compiler

and additions to

instruction set provide

25% code size reduction

Relative Value

6

5

4

3

2

1

0

SH-2

@50MHz

SH-2A

@160MHz

SH-2A

@200MHz

4.8x

6x

Relative Value

1

0.75

0.50

0.25

0

SH-2 @ 50MHz SH-2A @ 200MHz

1/25x

SH-2A

Relative Value

1

0.75

0.50

0.25

0

SH-2

0.75x

SH-2A Enhancements

TOP REASONS TO SELECT SuperH

91 Instructions103 Instructions

Instruction Set

Architecture

Shared BusSuperHyway

3 Independent

Buses

Greater Bandwidth

Bus Architecture

16/32 KB I/O Cache

2-Way

Set-Associative

32/32 KB I/O Cache

4-Way

Set-Associative

Larger Cache Size

5-Stage Pipeline10-Stage Pipeline

Improved FPU

Architecture

Superscalar

5-Stage Pipeline

Superscalar

7-Stage Pipeline

Improved Micro-

Architecture

240 MHz @ 1.5V600 MHz @ 1.25V

Higher Performance

at Lower Power

SH-4SH-4A

SH-4A Enhancements

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 41 42

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