Renesas SuperH SH7710 E10A Manual de usuario descargar pdf (Pagina 7)

Built in hardware

multiply-accumulate unit

• 16-bit x 16-bit + 42-bit

(SH-1 devices)

• 32-bit x 32-bit + 64-bit

(SH-2, SH-3, SH-4 chips)

Instruction execution

• Scalar architecture:

One instruction per clock cycle

• Superscalar architecture

(SH-2A/SH-4/SH-4A onwards):

Maximum of two instructions

per cycle

• 5-stage instruction pipeline

(7-stage in SH-4A)

Memory Management Unit

for RTOS (SH-3 and beyond)

• 4-Gbyte address space,

256 address space identifiers

(8-bit ASIDs)

• Single virtual mode and

multiple virtual memory mode

• Supports multiple page sizes:

1KB, 4KB, 64KB, 1MB

• 4-entry fully-associative TLB

for instructions

• 64-entry fully-associative TLB

for instructions and operands

• Supports software-controlled

replacement and random-

counter replacement algorithm

• TLB contents can be accessed

directly by address mapping

The SuperH Architecture

5

Parallel execution

of two instructions

Load/store unitInteger unitBranch unit

Decoder 1 Decoder 2

Floating point unit

(FE)(LS) (MT)(EX)(BR) (MT)

Instruction queue

Instruction queue

Instruction queue

Instruction queue

8 instruction x 16 bit

Inst. 1 Inst. 2

64 bit

SH-2A/SH-4/SH-4A Two-Way Superscalar Architecture

Data

Bypass

Data

Cache

Tags

Physical

RAM

Address

VPN offset

Virtual Address

MMU

TLB

0

1

2

127

Page

(1KB or 4 KB):

page boundary:

offset

PPN offset

Physical Address

TLB Miss

Handler

Paging

Routine

Page Tables

Swap Area

Mass Storage

MMU Block Diagram

Single Scalar

Superscalar

Clock

Instruction

A

Parallel processing

Execution

time = 1/2

Execution time

Instruction

A

Instruction

B

Instruction

C

Instruction

B

Instruction

C

Instruction

D

Instruction

D

······

···

···

Superscalar Operations

1 2 3 4 5 6 7 8 9 10 11 12 ... 41 42

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