Renesas SuperH SH7710 E10A Manual de usuario descargar pdf (Pagina 34)

Appendices

Buffer

ROM

SH-2

CPU

DSP

Y-RAM

User break

controller

Interrupt

controller

Bus state

controller

Clock pulse

generator

Serial

communication

interface

Motor

management

timer

Timer pulse

unit

Compare-match

timer

A/D converter

D/A converter

Watchdog

timer

I/O ports

External

bus interface

Internal address bus (CAB)

32-bit internal data bus (IDB)

Internal Y address bus

16-bit internal Y data bus

Internal X address bus

64-bit internal ROM bus

16-bit internal X data bus

Peripheral address bus

16-bit peripheral data bus

X-RAM

Operating mode

controller

Direct

memory access

controller

32-bit internal data bus (CDB)

Internal address bus (IAB)

= SH-DSP only

LEGEND:

CPG Clock Programmable Generator

ADC Analog to Digital Converter

DAC Digital to Analog Converter

TPU 16-Bit Timer Pulse Unit

WDT WatchDog Timer

MMT Motor Management Timer

MTU Multifunction Timer Pulse Unit

CMT Compare Match Timer

PWM Pulse Width Modulater

ATU Advanced Timer Unit

ATU-II Advanced Timer Unit-II

APC Advanced Pulse Controller

TIM 2 8-Bit Timer 2

HCAN Car Automotive Network

HCAN2 Car Automotive Network

SCI Serial Communication Interface

UDI User Debug Interface

DTC Data Transfer Controller

PFC Pin Function Controller

■ Appendix A-1: Architecture of SH-2 and SH2-DSP Series

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