Renesas SuperH SH7710 E10A Manual de usuario descargar pdf (Pagina 8)

6

SuperH

®

Family of Microcontrollers & Microprocessors

■ SuperH Hybrid RISC/DSP

Architectural Features

Instruction set upward compatible

with SuperH RISC chips

• Upward compatible with SuperH:

SH1, SH-2, SH-3 (for SH3-DSP)

• Compact 16/32-bit instruction

code (32-bit code only for DSP

instructions)

A single SH and DSP CPU engine

optimized for low power and cost

• Less than 5% power increase

from SH core (non-DSP)

• Less than a 10% size increase

from SH core (non-DSP)

• Unified program/data memory

for RISC and DSP operations

Full-featured 16-bit integer

DSP capabilities

• Executes four independent

parallel operations

• Single-cycle 16x16 operations

• Harvard architecture: accesses

one instruction and two data

words per cycle

• Zero overhead looping, circular

buffer, saturation arithmetic

Adds DSP performance to the

SuperH architecture

• Performs a real FIR algorithm

of T taps in T cycles

• Simultaneous access of

two data buses and one

instruction bus

DSP registers

• Two 40-bit data registers,

six 32-bit data registers

• Modulo register (MOD, 32 bits)

added to control registers

• Repeat counter (RC) added to

status registers (SR)

• Repeat start register (RS, 32-bit)

and repeat end register (RE, 32-bit)

added to control registers

Key DSP instructions

• Saturation arithmetic

– Prevents overflows and underflows

– Result that exceeds the

register width is set to the

max width of the register

(Ex: H’FF + H’01 = H’FF).

• Guard bits

– DSP execution unit has two

40-bit registers that provide an

additional 8 bits to accommodate

overflow/underflow results

• Independent add and multiply

operations

– Either multiply and then add on

the same data, or multiply and

add on two separate data

• Execute four independent

operations simultaneously

– multiply , add, mov x, mov y

– suited for performing FIR filters

Easier to program and simplified

product development

• Multitasking instead of

multiprocessing

• Eliminates inter-processor

communication

• Single hardware/software

design environment

DMAC RISC

or

DSP

Cache

(4-way

unified)

RISC

or

DSP(Y)

Memory

RISC

or

DSP(X)

Memory

Flexible Memory

for Data/Program

(2 banks for

each X and Y)

4-Bus Structure

Parallel execution of 1 program fetch and 2

data accesses • Background DMA-capable

SH RISC CPU decodes DSP instructions

Can generate three addresses for DSP instructions

or execute RISC instructions

DSP execution unit

General-purpose registers

file single-cycle MAC and

other DSP functions

LAB

IAB

XAB

YAB

32

32

16

16

32

32

16

16

Single CPU Engine with Two Execution Units

CONTROL SIGNAL

Decoder

16/32-bit

Pre-Fetch Unit

8 x 32-bit

Data Register File

ALU

ALU

16 x 32-bit

General-Purpose

Register File

Barrel

Shifter

ALU

MULT

XDB

YDB

LDB

DB

SH2-DSP Core Architecture

1 2 3 4 5 6 7 8 9 10 11 12 13 ... 41 42

Comentarios a estos manuales

Sin comentarios