Renesas SuperH SH7710 E10A Manual de usuario descargar pdf (Pagina 35)

33

Architecture Diagrams

CPU bus

(C bus)

(I clock)

SH-2A

CPU core

Cache

controller

Instruction

cache memory

8 Kbytes

Operand

cache memory

8 Kbytes

On-chip RAM

128 Kbytes

User break

controller

(UBC)

Bus state

controller

(BSC)

Peripheral

bus controller

Direct memory

access controller

(DMAC)

Pin function

controller

(PFC)

I/O ports

Clock pulse

generator (CPG)

Interrupt

controller

(INTC)

Multi-function

timer pulse

unit 2

subset

(MTU2S)

Multi-function

timer pulse

unit 2

(MTU2)

Port output

enable 2

(POE2)

Compare

match timer

(CMT)

CPU memory access bus (M bus)

Internal bus (I bus) (B clock)

Peripheral bus (P clock)

Port Port Port Port Port Port

General input/output EXTAL input,

XTAL output,

CKIO input/output,

Clock mode input

RES

input,

MRES

input,

NMI input,

IRQ input,

PINT input,

IRQOUT

output

Timer pulse

input/output

Timer pulse

input/output

POE

input

PortPort

Port

External bus input/output

External bus width mode input

UBCTRG

output

DREQ input

DACK output

TEND output

Watchdog

timer

(WDT)

Port

WDTOVF

output

Serial

communication

interface

with FIFO

(SCIF)

Port

Serial input/output

I

2

C bus

interface 3

(IIC3)

Port

I

2

C bus

input/output

A/D converter

(ADC)

Port

Analog input,

ADTRG

input

D/A converter

(DAC)

Port

Analog output

Power-down

mode

control

High-performance

user debugging

interface

(H-UDI)

Port

JTAG input/output

CPU instruction fetch bus (F bus)

■ Appendix A-2: Architecture of SH-2A Series

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