Renesas SuperH SH7710 E10A Manual de usuario descargar pdf (Pagina 16)

Peripherals

■ Peripheral Control Interconnect (PCI)

• Compatible with PCI bus operating

speeds of 33MHz/66MHz

• Compatible with 32-bit PCI bus

• Up to four PCI master devices running at

33MHz, or one PCI master device at

66MHz, can be connected

• Arbitration control is available as a PCI

host function

• Can operate as master or target

• When operating as master, PIO and

DMA transfer are available

• Four DMA transfer channels

• Six 32-bit x 16 longword internal FIFO

(one for target reading, one for target

writing, and four for DMA transfer)

• SRAM, DRAM, SDRAM, DDR-SDRAM,

and MPX can be used as external memory

for PCI bus data transfers

• 32-bit or 16-bit memory data bus for data

transfers with PCI bus (32-bit bus when

connected to SDRAM or DDR-SDRAM)

• Support for big-endian and little-endian

local bus (PCI bus operates with little

endian, while internal bus for peripheral

modules operates with big endian)

■ DMA Controller (DMAC)

• Up to twelve channels

• Choice of 8-bit, 16-bit, 32-bit, 64-bit, or

32-byte transfer data length

• Choice of address mode; single or dual;

choice of bus mode: cycle steal mode or

burst mode

• Two types of DMAC channel priority

ranking: fixed-priority mode and round-

robin mode

SuperH

Family of Microcontrollers & Microprocessors

Interrupt

Control

Local

PCI Bus

PCI

Configuration

PCI Bus Interface

Internal

Peripheral

Module Bus

Interface

Local

FIFO

32B (2 sides)6

Data Transfer Control

Local

Bus Request

Acknowledge

Local

PCIC Bus Controller

PCI Clock

33/66 MHz

(PCICLK)

Local Bus

Feedback

Input Clock

from CKIO

Local Bus Clock

(Bf ) Cycle: Bcyc

Interrupts

PCIC Module

(Peripheral Bus)

Internal Peripheral

Module Bus

PCI Block Diagram

DMAC

DACK

External

memory

External

device

with DACK

SuperH Device

External

address

bus

: Data flow

External

data bus

SINGLE-ADDRESS MODE: Parallel read and write

DUAL-ADDRESS MODE: Two-cycle read and write

Data Buffer

SAR

DAR

DMAC

BSC

SuperH device

Address bus

Data bus

Memory

Transfer Source

Module

2nd bus cycle: Taking the DAR value as the address, the data stored

in the BSC's data buffer is written to the transfer destination module.

1st bus cycle: Taking the SAR value as the address, data is read

from the transfer source module and stored temporarily in the

data buffer in the Bus State Controller (BSC).

Data Buffer

Address bus

Data bus

Memory

SAR

DAR

DMAC

BSC

SuperH device

Transfer Destination

Module

Transfer Destination

Module

Transfer Source

Module

DMAC: Single and Dual Address Modes

1 2 ... 11 12 13 14 15 16 17 18 19 20 21 ... 41 42

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Renesas SuperH SH7710 E10A Manual de usuario Pagina 16

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