Renesas SuperH SH7710 E10A Manual de usuario descargar pdf (Pagina 37)

35

Architecture Diagrams

CPU I-cache

LBSC

(External bus)

LEGEND:

AUD:

CMT:

CPG:

CPU:

DDRIF:

DMAC:

FLCTL:

FPU:

GPIO:

HAC:

HPB:

HSPI:

H-UDI:

I-Cache:

INTC:

LBSC:

LRAM:

MMCIF:

MMU:

O-Cache:

PCIC:

RTC:

Advanced user debugger

Timer/counter

Clock pulse generator

Central processing unit

DDR-SDRAM interface

Direct memory access controller

NAND flash memory controller

Floating-point unit

General purpose I/O

Audio codec

Peripheral bus bridge

Serial protocol interface

User debugging interface

Instruction cache

Interrupt controller

Local bus state controller

L memory

Multimedia card interface

Memory management unit

Operand (data) cache

PCI controller

Realtime clock

SCIF:

SIOF:

SSI:

SuperHyway RAM:

TMU:

UBC:

WDT:

Serial communication interface with FIFO

Serial I/O with FIFO

Serial sound interface

SuperHyway memory

Timer unit

User break controller

Watchdog timer

FPU

MMU

O-cache

LRAM

SH-4A core

UBC

AUD

Instruction bus

Operand bus

DDRIF

(External bus)

PCIC

(External bus)

I/O

multiplexed

I/O

multiplexed

I/O

multiplexed

HPB

TMU

SCIF

channel 0

HSPI

FLCTL

SCIF

channel 1

MMCIF

SIOF

HAC

SSI

GPIO

CPG

WDT

RTC

CMT

H-UDI

INTC

DMAC

SuperHyway

RAM

SuperHyway

router

Peripheral bus

SuperHyway bus

■ Appendix A-4: Architecture of SH-4A Series

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